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CAT25080, CAT25160
READ OPERATIONS
Read from Memory Array
To read from memory, the host sends a READ instruction
followed by a 16 ? bit address (see Table 13 for the number
of significant address bits).
After receiving the last address bit, the CAT25080/160
will respond by shifting out data on the SO pin (as shown in
Figure 9). Sequentially stored data can be read out by simply
continuing to run the clock. The internal address pointer is
automatically incremented to the next higher address as data
is shifted out. After reaching the highest memory address,
the address counter “rolls over” to the lowest memory
address, and the read cycle can be continued indefinitely.
The read operation is terminated by taking CS high.
Read Status Register
To read the status register, the host simply sends a RDSR
command. After receiving the last bit of the command, the
CAT25080/160 will shift out the contents of the status
register on the SO pin (Figure 10). The status register may
be read at any time, including during an internal write cycle.
While the internal write cycle is in progress, the RDSR
command will output the full content of the status register
(New product, Rev. D) or the RDY (Ready) bit only (i.e.,
data out = FFh) for previous product revision C (Mature
product). For easy detection of the internal write cycle
completion, both during writing to the memory array and to
the status register, we recommend sampling the RDY bit
only through the polling routine. After detecting the RDY bit
“0”, the next RDSR instruction will always output the
expected content of the status register.
CS
0
1
2
3
4
5
6
7
8
9
10
20 21
22 23
24
25
26 27
28 29
30
SCK
OPCODE
BYTE ADDRESS*
SI
0
0
0
0
0
0
1
1
A N
A 0
SO
HIGH IMPEDANCE
7
6
5
DATA OUT
4 3 2
1
0
CS
Dashed Line = mode (1, 1)
* Please check the Byte Address Table (Table 13)
Figure 9. READ Timing
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SCK
OPCODE
SI
0
0
0
0
0
1
0
1
SO
HIGH IMPEDANCE
7
6
5
4
DATA OUT
3
2
1
0
Dashed Line = mode (1, 1)
MSB
Figure 10. RDSR Timing
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